View STW5095_1266918.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. rev 1.0 november 2005 1/69 2 STW5095 low power asynchronous stereo audio codec with integrated power amplifiers features 20 bit audio resolution, 8khz to 96khz independent rate adc and dac asynchronous sampling adc and dac: they do not require oversampled clock and information on the audio data sampling frequency (fs). jitter tolerant fs wide master clock range: from 4mhz to 32mhz i 2 c/spi compatible control i/f stereo headphones drivers, handsfree loudspeaker driver, line out drivers mixable analog line inputs voice filters: 8/16khz with voice channel filters automatic gain control for microphone and line- in inputs two programmable master/slave serial audio data interfaces (i 2 s, spi, pcm compatible and other formats) frequency programmable clock outputs multibit ? modulators with data weighted averaging adc and dac dsp functions for bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter and dynamic compression. 93 db dynamic range adc, 0.001% thd with full scale output @ 2.7v 95 db dynamic range dac, 0.02% thd performance @ 2.7v over 16 ? load analog inputs selectable stereo differential or single-ended microphone amplifier inputs with 51db range programmable gain one microphone biasing output microphone plug-in and push-button detection input selectable stereo differential or single-ended line inputs with 38 db range programmable gain analog output drivers stereo headphones outputs driving capability: 40 mw (0.1% thd) over 16 ? with 40 db range programmable gain common mode voltage headphones driver (phantom ground) balanced loudspeaker output driving capability: up to 500m w (v ccls >3.5v; 1% thd) over 8 ? with 30db range programmable gain transient supression filter during power up and power down balanced/unbalanced stereo line outputs driving capability 1k ? applications digital cellular telephones with mp3 player, stereo recorder, fm radio stereo listening and recording functions, live music recording portable digital players and recorders STW5095 tfbga64 5x5 (64 pins) www.st.com .com .com .com 4 .com u datasheet
STW5095 2/69 description STW5095 is a low power asynchronous stereo audio codec device with headphones amplifiers for high quality audio listening and recording. the STW5095 control registers are accessed through a selectable i 2 c-bus compatible or spi compatible interface. the STW5095 asynchronous stereo audio codec is designed to easily fit in most audio systems because it supports an extended master clock range (any value between 4 mhz and 32 mhz) and at the same time it supports any audio data rate (independent in ad and da paths) from 8 khz to 48 khz and from 88 khz to 96 khz, moreover it can tolerate jitter on audio data without degrading performance. the audio data serial interfaces (for ad and da) can be master or slave, are i 2 s compatible and they support other formats that can easily interface to standard serial ports. the two audio interfaces can be used as a single bidirectional interface. two frequency programmable clock sources are available to generate the master clock for the audio sub-system of other devices. the internal d to a and a to d converters work with up to 24 bit resolution. the supply voltage can be the same for the whole device, in the range 2.4 v to 2.7 v, or it can be differentiated for digital (v cc : 1.8 v to 2.7 v), analog (v cca : 2.4 v to 3.3 v) and loudspeaker driver (v ccls : v cca to 5.5 v) to obtain best performance and maximum power to the loudspeaker (up to 500 mw). STW5095 has multiple analog mixable inputs and outputs. it can directly drive stereo headphones without external capacitors and it has a loudspeaker driver that can also be used for monophonic group listening. stereo differential and single ended microphones, auxiliary line in stereo and mono signals can be mixed and connected to the adc or directly to the drivers, mixed also with dac audio signals. STW5095 stereo audio codec main applications include multimedia handheld devices such as cellular phones with added low-power high- quality mp3 and ? or fm radio listening/recording features, or any battery powered equipment such as pdas, camcorders, etc. that require stereo audio codec with headphones drivers. ordering codes pin configuration (top view) part number details STW5095 tfbga 64 tray STW5095t tfbga 64 tape and reel a b c d e f g h 12345678 sda/sdin vcc vcca hdet da_ck ad_data da_sync irq da_ock ad_ock sclk gnd ad_ck amck ad_sync da_data cmod vcca micln aux1l as/csb vcc gnd mbias gnda aux3l miclp capmic vccio vcca micrn aux1r capls lineinl aux2lp aux2ln aux3r gnda caplinein micrp lsps vcmhps gndcm oln lsns lineinr aux2rp aux2rn lsp vcmhp gndp olp lsn vccp gndp orn gndp vccls hpl vccp gndp vccls hpr orp .com .com .com .com 4 .com u datasheet
STW5095 3/69 contents 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 clock generators and master mode function . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 audio digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9 analog output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 analog mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11 ad path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.12 da path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.13 analog-only operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.14 automatic gain control (agc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.15 interrupt request: irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.16 headset plug-in and push-button detection . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.17 microphone biasing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 supply and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 dsp control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5 analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.6 digital audio interfaces master mode and clock generators . . . . . . . . . . . . . 32 4.7 digital audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.8 digital filters, software reset and master clock control . . . . . . . . . . . . . . . . . 36 .com .com .com .com 4 .com u datasheet
STW5095 4/69 4.9 interrupt control and control interface spi out mode . . . . . . . . . . . . . . . . . . 37 4.10 agc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 control interface and master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 control interface i2c mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2 control interface spi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3 master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6 audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8 operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2 operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.4 typical power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2 amck with sinusoidal input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.3 analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.4 headset plug-in and push-button detector . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.5 microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.6 power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.7 ls gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10 analog input/output operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1 analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2 microphone input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.3 line input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.4 line output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.5 power output levels hp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.6 power output levels ls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 .com .com .com .com 4 .com u datasheet
STW5095 5/69 11 stereo audio adc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12 stereo audio dac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13 ad to da mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . . . 61 14 stereo analog-only path specific ations . . . . . . . . . . . . . . . . . . . . . . . . . . 61 15 adc (tx) & dac (rx) specifications wi th voice filters selected . . . . . 62 16 typical performance plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 17 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 .com .com .com .com 4 .com u datasheet
1 functional block diagram STW5095 6/69 1 functional block diagram note: this diagram shows the functionality of the device and of some control registers bits but it does not necessarily reflect the exact hardware implementation. figure 1. STW5095 block diagram mck ad sample rate converter da sample rate converter transient suppr. filter transient suppr. filter bandgap ck gen/ master mode digital da-pll pll control logic power-on reset registers control i/f digital ad-pll audio ad-i/f headset detection transient suppr. filter left lineout -40:0 db step 2 -40:0 db step 2 right driver log: -18:0 db step 3 right lineout vccio gnd vcc gndcm gndp vccls vccp gnda vcca l (l+r)/2 r stereo diff. stereo sing.e. stereo sing.e. stereo diff. stereo sing.e. comm. mode currentbias stereo dac STW5095 left driver cm driver voltage reference -20 : +18 db step 2 -24 : 6 db step 2 mono driver miclo lssel mixlin mixmic admic adlin irq gen ad_sync caplinein capmic lineinl lineinr aux3r aux3l aux2nr aux2pr aux2nl aux2pl aux1r aux1l micrn micrp micln miclp mbias vcmhp vcmhps olp oln hpl lsps lsp capls lsn lsns hpr orp orn ad_ck ad_data cmod as/csb sclk sda/sdin hdet irq ad_ock amck da_ock da_sync da_ck da_data oscillator mic. bias dsp ad to da mixing gain agc (mic&lin) admono damono (sidetone) dac digital gain adc digital gain dyn.comp. bass treble (audio only) da to ad mixing gain (audio only) adrtol stereo adc filter audio/voice filter audio/voice dac mixdac ? modulator analog filter ? adc linein aux1 aux2 aux3 mute lin l-r amps linsel linlg linrg stereo path audio da-i/f da_sync ad_sync 2.1v reference agc (from dsp) agc (from dsp) rl lsg hplg hprg 0 39 db step 1.5 mic aux1 aux2 aux3 mute mic l-r preamps micsel miclg micrg -12 0 db step 1.5 micla micra ck gen/ master mode l r l r .com .com .com .com 4 .com u datasheet
STW5095 2 pin description 7/69 2 pin description table 1. pin description pin n name type description d2 c2 e8 d7 miclp micln micrp micrn ai left and right channel differential pins for microphone input. c8 mbias ao microphone biasing pin. fixed voltage reference. d1 capmic ai a capacitor must be connected between capmic and ground. c1 d8 aux1l aux1r ai left and right channel single ended pins for microphone or line input. e2 e1 f7 f8 aux2lp aux2ln aux2rp aux2rn ai left and right channel differential pins for microphone or line input. d3 e5 aux3l aux3r ai left and right channel single ended pins for microphone or line input. e3 f6 lineinl lineinr ai left and right channel single ended pins for line input. e7 caplinein ai a capacitor must be connected between caplinein and ground. g4 g5 lsp, lsn ao analog differential loudspeaker amplifier output for left channel or right channel or the sum of both. this output can drive 50nf (with series resistor) or directly an earpiece transductor of 8 ? ; it can deliver up to 500mw. f4 f5 lsps, lsns ao lsps, lsns (sense) pins must be connected on the application board to lsp, lsn pins respectively (see application note). the connection must be as close as possible to the pins. e4 capls ai a capacitor can be connected between this node and ground. see application notes h2 h7 hpl hpr ao audio single ended headphones amplifier outputs for left and right channels. the outputs can drive 50nf (with series resistor) or directly an earpiece transductor of 16 ? . g3 vcmhp ao common mode voltage headphones output. the negative pins of headphones left and right speakers can be connected to this pin to avoid decoupling capacitors. f3 vcmhps ao vcmhps (sense) pin must be connected on the application board to vcmhp pin (see application note). the connection must be as close as possible to the pins. g1 f1 h8 g8 olp oln orp orn ao audio differential line out amplifier for left and right channels. this outputs can drive up to 1k ? resistive load. can be used as single ended outputs. .com .com .com .com 4 .com u datasheet
2 pin description STW5095 8/69 c4 cmod di control interface type selector : i 2 c-bus mode or spi mode. a2 sclk di control interface serial clock input. b4 sda/sdin diod control interface serial data input-output in i 2 c mode (sda), control interface serial data input in spi mode (sdin). c5 as/csb di control interface address select in i 2 c mode (as). interface enable signal in spi mode (csb). a7 ad_sync dio frame sync for stereo a/d converter. b7 da_sync dio frame sync for stereo d/a converter. a5 ad_ck dio serial data clock for stereo a/d converter. b5 da_ck dio serial data clock for stereo d/a converter. b6 ad_data do serial data out for stereo a/d converter. a8 da_data di serial data in for stereo d/a converter. b1 hdet ai headset detection input (microphone plug-in and push-button detection). b8 irq do programmable interrupt output. active low signal. a3 ad_ock do oversampled clock out from ad clock generator. a4 da_ock do oversampled clock out from da clock generator. a6 amck di ai master clock input. accepted range 4 mhz to 32 mhz. amck is a digital square wave amck is an analog sinewave (see amcksin section 4.8 on page 36 ) b2 c3 d6 vcca p power supply pins for the analog section. standard operating range: from 2.7 v to 3.3 v low voltage (lv) range: from 2.4 v to 2.7 v d4 e6 gnda p ground pins for the analog section. f2 gndcm p ground pin for analog reference. gndcm can be connected to gnda. g6 h1 vccp p power supply pins for the left and right output drivers (headphones and line-out). operating range: from v cca to 3.3v h3 h6 vccls p power supply pins for the mono differential output driver. operating range: from v cca to 5.5v g2 g7 h4 h5 gndp p ground pins for the left, right and mono-differential output drivers. gndp and gnda must be connected together. b3 c6 vcc p power supply pins for the digital section. operating range: from 1.71 v to 2.7 v table 1. pin description pin n name type description .com .com .com .com 4 .com u datasheet
STW5095 2 pin description 9/69 note: vcc, vcca, vccp, vccls can be connected together for low cost applications: operating range: 2.4 v-2.7 v. type definitions a1 c7 gnd p ground pins for the digital section. d5 vccio p power supply pin for the digital i/o buffers. operating ranges: from 1.2 v to 1.8 v and from 1.71 v to v cc ai - analog input ao - analog output aio - analog input output di - digital input do - digital output dio - digital input output diod - digital input output open drain p - power supply or ground table 1. pin description pin n name type description .com .com .com .com 4 .com u datasheet
3 functional description STW5095 10/69 3 functional description 3.1 power supply STW5095 can have different supply voltages for different blocks, to optimize performance, power consumption and connectivity. see operative supply voltage on page 50 for voltage definition. the correct sequence to apply supply voltage is to set first (and unset last) the digital i/o supply (v ccio ). the other supply voltages can be set in any order and can be disconnected individually, if needed. disconnection does not cause any harm to the device and no extra current is pulled from any supply during this operation. moreover if a voltage conflict is detected, like v cca < v cc (not allowed), simply all blocks connected to v cca are set to power down and no extra current is pulled from supply. when v ccio is set and v cc (digital supply) is not set, all the digital output pins are in high impedance state, while the digital inputs are disconnected to avoid power consumption for any input voltage value between gnd and v ccio . before v cc is disconnected the device has to be reset (swres bit in cr30). when the analog supply (v cca ) is set and v cc is not set, all the analog inputs are in high impedance state. the control registers are powered by vcc pin (digital supply) so if this pin is disconnected all the information stored in control registers is lost. when the digital supply voltage is set, a power-on-reset (por) circuit sets all the registers content to the default value and then generates an irq signal writing 1 in bits pormsk and porev in cr31 and cr32 respectively. all supplies must be on during operation. 3.2 device programming STW5095 can be programmed by writing control registers with spi or i 2 c compatible control interface (both slave). the interface is always active, there is no need to have the master clock running to program the device registers. the choice between the two interfaces is done via an input pin (cmod): 1. cmod connected to gnd: i 2 c compatible mode selected the device address is selected with as pin: when this mode is selected control registers are accessed through pins: sclk (clock) sda (serial data out/in, open drain) 2. cmod connected to v ccio : spi compatible mode selected when this mode is selected control registers are accessed through: csb (chip select, active low) sclk (clock) sdin (serial data in) ad_ock or da_ock or irq (serial data out, if selected) as connected to gnd: chip address 001101 0 1(35hex) for reading, 001101 0 0 (34hex) for writing as connected to v ccio : chip address 001101 1 1(37hex) for reading, 001101 1 0 (36hex) for writing .com .com .com .com 4 .com u datasheet
STW5095 3 functional description 11/69 device programming: i 2 c . the i 2 c control interface timing is shown in section 5.1 on page 41 . the interface has an internal counter that keeps the current address of the control register to be read or written. at each write access of the interface the address counter is loaded with the data of the register address field. the value in the address counter is increased after each data byte read or write. it is possible to access the interface in 2 modes: single-byte mode in which the address and data of a single register are specified, and multi-byte mode in which the address of the first register to be written or read is specified and all the following bytes exchanged are the data of successive registers starting from the one specified (in multi-byte mode the internal address counter restart from register 0 after the last register 36). using the multi-byte mode it is possible to write or read all the registers with a single access to the device on the i 2 c bus. device programming: spi. the spi control interface timing is shown in section 5.2 on page 42 . bits spiosel (spi output select) in cr33 control the out pin selection for serial data out (none, ad_ock, da_ock or irq), while bit spiohiz=1 in cr33 selects the high impedance state of serial data out pin when idle. the first bit sent on sdin, after csb falling edge, sets the interface for writing (sdin=1) or reading (sdin=0), then a 7-bit control register address follows. if the interface is set for writing then the last 8 bits on sdin are written in the control register. if the interface is set for reading then after the 7 bit address STW5095 sends out 8 bits data on the pin selected with bits spiosel in cr33, while bits present at sdin pin are ignored. if spiosel=00 (no out pin selected) the reading access on spi interface can still be useful to clear the irq event bits in cr32. .com .com .com .com 4 .com u datasheet
3 functional description STW5095 12/69 3.3 power up STW5095 internal blocks can individually be switched on and off according to the user needs. a general power up bit is present at bit 7 of cr0. see the following drawing to select the needed block for the desired function. a fast-settling function is activated to quickly charge external capacitors when the device is switched on (capls, caplinein and capmic). 3.4 master clock the master clock pin (amck) accepts any frequency from 4 mhz to 32 mhz. the 4-32 mhz range is divided in sub-ranges that have to be programmed in bits ckrange in cr30. the jitter and spectral properties of this clock have a direct impact on the dac and adc performance because it is used to directly or by integer division drive the continuous-time to sampled-time interfaces. note that amck clock des not need to have any relation to any other digital or analog input or output. figure 2. power up block diagram powerup enana STW5095 enmixl enmixl enhpvcm enhpl enls enhpr enmicr enmicl enlinr enlinl enosc enadcr enadcl endacr endacl audio i/f enlol enlor enhsd enpll damast endaock admast enadock mbias enamck endackgen enadckgen enosc =1 enosc =0 .com .com .com .com 4 .com u datasheet
STW5095 3 functional description 13/69 amck can be either a squarewave or a sinewave, bit amcksin in cr30 selects the proper input mode. when a sinewave is used as input, amck pin must be decoupled with a capacitor. specification for sinusoidal input can be found in section 9.2: amck with sinusoidal input on page 53 . the amck clock is not needed when only analog functions are used. for this purpose an internal oscillator with no external components can be used to operate the device (see analog-only operation on page 17 ). 3.5 data rates STW5095 supports any data rate in 2 ranges: 8 khz to 48 khz and 88 khz to 96 khz. the range is selected with bits da96k and ad96k in cr29 for ad and da paths respectively. note: when ad96k=1 it is required to have da96k=1. the rates are fully independent in a/d and d/a paths. moreover the rates do not have to be specified to the device and they can change on the fly, within one range, while data is flowing. the 2 audio data interfaces (for a/d and d/a) can independently operate in master or slave mode. 3.6 clock generators and master mode function STW5095 provides 2 internal clock generators that can drive, if needed, the audio interfaces (master mode), and/or two independent master clocks. the amck clock input frequency is internally raised via a pll to obtain a clock (mck) in the range 32 mhz to 48 mhz. the ratio mck/amck is defined in cr30 (see mckcoeff in section 4.6 on page 32 ). mck is used to obtain, by fractional division, the oversampled clock (ock), word clock (sync) and bit clock (ck), that will therefore have edges aligned with mck (the ock period can have jitter of 1 mck period). the frequency of ock, sync and ck is set with daockf in cr21/20 for da interface, and adockf in cr24/23 for ad interface. the ratio between ock and sync clocks is selected with bit daock512 in cr22 for da interface and bit adock512 in cr25 for ad interface. the ratio between ck and sync clocks depends on the selected interface format (see audio digital interfaces paragraph below). note that spi format can only be slave. the adock and daock output clocks are activated by bits enadock and endaock respectively, while master mode generation is activated with two bits: first admast (damast) sets adsync and adck (dasync and dack) pins as outputs, then admastgen (damastgen) generates the sync and ck clocks. the logical value at sync and ck pins before data generation depends on the interface selected format. see description of cr20 to cr25 for further details. .com .com .com .com 4 .com u datasheet
3 functional description STW5095 14/69 3.7 audio digital interfaces two separate audio data interfaces are provided for ad and da paths to have maximum flexibility in communicating with other devices. the 2 interfaces can have different rates and can work in different formats and modes (i.e ad interface can be 8 khz pcm slave while da is 44.1 khz i 2 s master). the pins used by the interfaces are: ad_sync, ad_ck and ad_data for ad path word clock, bit clock and data, respectively, and da_sync, da_ck and da_data for da path word clock, bit clock and data, respectively. data is exchanged with msb first and left channel data first in all formats. data word-length is selected with bits dawl in cr26 and adwl in cr27. ad_data pin, outside the selected time slot, is in the impedance condition selected by bit adhiz in cr28 in all data formats except right-aligned-format. in the following paragraphs sync, ck and data will be used when the distinction between ad and da is not relevant. when master mode is selected (bits damast and admast in cr22 and cr25 respectively) the sync and ck clocks are generated internally. in addition, an oversampled clock can be generated for each interface (ad_ock and da_ock). the ock clock is available in slave mode also, if needed. the ad and da interfaces can also be used as a single bidirectional interface when they are configured with the same format (delayed, dsp, etc.) and ad_sync is connected to da_sync and da_ck to ad_ck. master mode is still available selecting admast or damast (not both). the interfaces features are controlled with control registers cr26, cr27 and cr28. supported operating formats: delayed - format (i 2 s compatible) (daform or adform =000): the audio interface is i 2 s compatible ( figure 8 on page 45 ). the number of ck periods within one sync period is not relevant, as long as enough ck periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. ck can be either a continuous clock or a sequence of bursts. in master mode there are 32 ck periods per sync period (that means 16 ck periods per channel) when the word length is 16 bit, while there are 64 ck periods per sync period (or 32 ck periods per channel) when word length is 18bit or higher. bits adsyncp, dasyncp and adckp, dackp affect the interface format inverting the polarity of sync and ck pins respectively. left - aligned - format (daform or adform =001): this format is equivalent to delayed-format without the 1 bit clock delay at the beginning of each frame ( figure 8 on page 45 ). right - aligned - format (daform or adform =010): this format is equivalent to delayed-format, except that the audio data is right aligned and that the number of ck periods is fixed to 64 for each sync period ( figure 8 on page 45 ). dsp - format (daform or adform =011) in this format the audio interface starting from a frame sync pulse on sync receives (da) or sends (ad) the left and right data one after the other ( figure 9 on page 46 ). the number of ck periods within one sync period is not relevant, as long as enough ck periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. ck can be either a continuous clock or a sequence of bursts. in master mode there are 32 ck periods per sync period when the word length is 16 bit, while there are 64 ck periods per sync period when word length is 18bit or higher. bit ckp (adckp and dackp) affects the interface format inverting the polarity of ck pin. bit syncp (adsyncp and dasyncp) switches between .com .com .com .com 4 .com u datasheet
STW5095 3 functional description 15/69 delayed (syncp=0) and non delayed (syncp=1) formats. dsp-format is suited to interface with a multi-channel serial port. spi - format (daform or adform =100) in this format left and right data is received with separate data burst. every burst is identified with a low level on sync signal ( figure 9 on page 46 ). there is no timing difference between the left and right data burst: the two channels are identified by the startup order: the first burst after ad path or da path power-up identifies the left channel data, the second one is the right channel data, then left and right data repeat one after the other. ck must have 16 periods per channel in case of 16 bit data word and 32 periods per channel in case of 18 bit to 32 bit data word. the spi interface can be configured as a single-channel (mono) interface with bit spim (adspim and daspim). the mono interface always exchanges the left channel sample. spi-format can only be slave: if master mode is selected the ck and sync pins are set to 0. bit ckp (adckp and dackp) affects the interface format inverting the polarity of ck pin. pcm - format (daform or adform =111): this format is monophonic, as it can only receive (da) and transmit (ad) single channel data ( figure 9 on page 46 ). it is mainly used when voice filters are selected. if audio filters are used then the same sample is sent from da-pcm interface to both channel of da path, and the left channel sample from ad path is sent to ad-pcm interface. if in the ad path the right channel has to be sent to the pcm interface then the following must be set: adrtol=1 (cr27) and enadcl=0 (cr1). in master mode the number of ck periods per sync period is between 16 and 512 (see dapcmf in cr22 and adpcmf in cr25, section 4.6 on page 32 for details). bit ckp (adckp and dackp) affects the interface format inverting the polarity of ck pin. bit syncp (adsyncp and dasyncp) switches between delayed (syncp=0) and non delayed (syncp=1) formats. 3.8 analog inputs STW5095 has a stereo microphone preamplifier and a stereo line in amplifier, with inputs selectable among 5: mic (for microphone preamplifier only), linein (for line in amplifier only) and 3 different aux inputs (for microphone and line in amplifiers). the aux inputs can be used simultaneously for line in amplifiers and microphone preamplifiers. microphone preamplifier: it has a very low noise input, specifically designed for low amplitude signals. for this reason it has a high input gain (up to 39 db) keeping a constant 50 k ? input impedance for the whole gain range. however it can also be used as a line in preamplifier because it can accept a high dynamic input signal (up to 4 v pp ). there are two separate gain and attenuation stages in order to improve the s/n ratio when the preamplifier output range is below full scale (volume control).the gain and attenuation controls are separate for left and right channel (cr3 and cr4 respectively). the preamplifier input is selected with bits micsel in cr18, and it is disconnected when micmute=1. if a single ended input is selected then the preamplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to capmic pin, which has to be connected through a capacitor to a low noise ground (typically the same reference ground of the input). the stereo microphone preamplifier is powered up with bits enmicl and enmicr in cr1. line in amplifier: it is designed for high level input signal. the input gain is in the range -20 db up to 18 db. the line in amplifier input is selected with bits linsel in cr18, and it is disconnected when linmute=1. if a single ended input is selected then the amplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to caplinein pin, which has to be connected through a capacitor to a .com .com .com .com 4 .com u datasheet
3 functional description STW5095 16/69 low noise ground (typically the same reference ground of the input). the stereo line in amplifier is powered up with bits enlinl and enlinr in cr1. 3.9 analog output drivers STW5095 provides 3 different analog signal outputs and 1 common mode reference output: line out drivers: it is a stereo differential output, it can be used as single-ended output just by using the positive or negative pin. it can drive 1 k ? resistive load. the load can be connected between the positive and negative pins or between one pin and ground through a decoupling capacitor. the output gain is regulated with log bits in cr7, in the range 0 to -18 db, simultaneously for left and right channels. when used as a single ended output the effective gain is 6 db lower. it is muted with bit mutelo in cr19. the input signal of this stereo output can come from the analog mixer or directly from mic preamplifiers. the output common mode voltage level is controlled with bits vcml in cr19. the supply voltage of line out drivers is v ccp . the line out drivers are powered up with bits enlol and enlor in cr1. the output pins are in high impedance state with a 180k ? pull-down resistor when the line out drivers are powered down. headphones drivers: it is a stereo single ended output. it can drive 16 ohm resistive load and deliver up to 40 mw. the output gain is regulated with hplg and hprg bits in cr8 and cr9 respectively, with a range of -40 to 6 db. it is muted with bit mutehp in cr19. the input signal of this stereo output comes from the analog mixer.the output common mode voltage is controlled with bits vcml in cr19. the supply voltage of headphones drivers is v ccp . the headphones drivers are powered up with bits enhpl and enhpr in cr2.the output pins are in high impedance state when the headphones drivers are powered down. common mode voltage driver: it is a single ended output with output voltage value selectable with bits vcml in cr19, from 1.2 v to 1.65 v in steps of 150 mv. the output voltage should be set to the value closest to v ccp /2 to optimize output drivers performance. the common mode voltage driver is designed to be connected to the common pin of stereo headphones, so that decoupling capacitors are not needed at hpl and hpr outputs. the supply voltage of the common mode voltage driver is v ccp . the common mode voltage driver is powered up with bit enhpvcm in cr2.the output pin is in high impedance state when the common mode voltage driver is powered down. loudspeaker driver: it is a monophonic differential output. it can drive 8 ? resistive load and deliver up to 500 mw to the load. the output gain is regulated with lsg bits in cr7, in the range -24 to +6 db. the input signal of the loudspeaker driver comes from the analog mixers: bits lssel in cr29 select left channel, right channel, (l+r)/2 (mono) or mute. the output common mode voltage is obtained with an internal voltage divider from v ccls and it is connected to capls pin. the supply voltage of the loudspeaker driver is v ccls . the loudspeaker driver is powered up with bit enls in cr2.the output pin is in high impedance state when the loudspeaker driver is powered down. note: note on direct connection of v ccls to the battery: the voltage of batteries of handheld devices during charging is usually below 5.5 v, making v ccls supply pin suitable for a direct connection to the battery. in this case if STW5095 is delivering the maximum power to the load and the ambient temperature is above 70 c then the simultaneous charging of the battery can overheat the device. a basic protection scheme is implemented in STW5095 (activated with bit lslim in cr19): it limits the maximum gain of the .com .com .com .com 4 .com u datasheet
STW5095 3 functional description 17/69 loudspeaker to -6 db when v ccls is above 4.2 v, and it removes the limit for v ccls below 4.0 v. the loudspeaker gain is left unchanged if it is set below -6 db with bits lsg. this event (v ccls > 4.2 v) can generate, if enabled (bit vlsmsk in cr31), an irq signal. 3.10 analog mixer STW5095 can send to the output drivers the sum of stereo audio signals from 3 different sources, da path (bit mixdac in cr17), microphone preamplifiers (bit mixmic in cr17) and line in amplifiers (bit mixlin in cr17). the mixer does not have a gain control on the inputs, therefore the user should reduce the levels of the input signals within the analog signal range. the stereo analog mixer is powered up with bits enmixl and enmixr in cr2. 3.11 ad path the ad path converts audio signals from microphone preamplifiers (selected with bit admic in cr17) and line in amplifiers (bit adlin in cr17) inputs to digital domain. if both inputs are selected then the sum of the two is converted. after ad conversion the audio data is resampled with a sample rate converter and then processed with the internal dsp. two different filters are selectable in the dsp (bit advoice in cr29): stereo audio filter, with dc offset removal and fir image filtering; and a standard mono voice-channel filter (uses left channel input and feeds both channel output). the ad path includes a digital gain control (adclg, adcrg in cr12 and cr13 respectively) in the range -57 to +8 db. the maximum gain from mic preamplifier to ad interface is then 47 db. when audio filter is selected in both ad and da paths then da audio data can be summed to ad data and sent to the ad audio interface (see da2adg in cr15). left and right channels can be independently switched on and off to save power, if needed (bits enadcl and enadcr in cr1) 3.12 da path the da path converts digital data from the digital audio interface to analog domain and feeds it to the analog mixer. incoming audio data is processed with a dsp where different filters are selectable (bit davoice in cr29): audio filter, stereo, with fir image filtering, bass and treble controls (bits bass and treble in cr14), de-emphasis filter; and a standard voice-channel filter, mono (uses left channel input and feeds both channel output). a dynamic compression function is available for both audio and voice filters (bit dync in cr14). the da path includes a digital gain control (daclg, dacrg in cr10 and cr11 respectively) in the range -65 to 0 db. ad to da mixing (sidetone) can be enabled: see cr16 for details. left and right channel can be independently switched on and off to save power, if needed (bits endacl and endacr in cr1) 3.13 analog - only operation STW5095 can operate without amck master clock if analog-only functions are used. it is possible to mix microphone and line in preamplifiers signals and listen through headphones, loudspeaker or send them to line-out. the analog-only operation is enabled with bit enosc in cr0. when enosc=1 the ad and da paths cannot be used. .com .com .com .com 4 .com u datasheet
3 functional description STW5095 18/69 in analog mode STW5095 can handle two different stereo audio signals, so it can be used as a front end for an external voice codec that does not include microphone preamplifiers and power drivers: mic signal is sent through microphone preamplifiers directly to line out drivers (transmit path), while receive signal is sent through line in amplifiers to the selected power drivers. 3.14 automatic gain control (agc) STW5095 provides a digital automatic gain control in ad path. the circuit can control the input gain at mic preamplifier, line in amplifier or both (bits enagcmic and enagclin in cr35). when one input is selected, the center gain value used for the input is fixed with bits miclg, micrg, linlg and linrg in cr3 to cr6 (like in normal operation), then the agc circuit adds to all the gains a value in the range -10.5 db to +10.5 db (or, extended with bit agcrange in cr35, -21 db to 21 db), in order to obtain an average level at the digital interface output in the range -6 db to -30 db (selected with bits agclev in cr35). the agc added gain acts directly in the input gain, to avoid input saturation and improve s/n ratio, so it cannot exceed the input gain range. when mic and line-in inputs are selected simultaneously the control is performed on the sum of the two, preserving the balance fixed with input gains. different values for attack and decay constants can be selected, depending on the kind of signal the agc has to control (i.e. voice, music). the attack and decay time constants are related to the ad data rate (see bits agcatt and agcdel in cr34). 3.15 interrupt request: irq pin STW5095 interrupt request feature can signal to a control device the occurrence of particular events. two control registers are used to choose the behavior of irq pin: the first is a status/ event register (cr32), where bits can represent the status of an internal function (i.e. a voltage is above or below a threshold) or an event (i.e. a voltage changed crossing a threshold); the second is a mask register (cr31) where if a bit in the mask is set to 1 then the corresponding bit in the status/event register can affect irq pin status. the irq pin is always active low. at v cc power up an interrupt request is generated by the power-on-reset circuit that sets to 1 bits pormsk in cr31 and porev in cr32. after this event the pormsk bit should be cleared by the user and bit irqcmos in cr33 should be set according to the application (open drain or cmos). when an irq event occurs and spi control interface is selected with no serial output pin it is still possible to identify the event (and relative status) that generated the interrupt request. this can be done by setting the irq mask/enable bits (in cr31) one at the time (with successive writings) and reading the irq pin status. a simple example of this is the headset plug-in detection: at first we set bit hsdetmsk=1 in cr31 (with all the other bits set to 0). if there is an interrupt request then we set hsdetmsk=0 and hsdeten=1, so we can read the hsdet status at irq pin. then we read cr32 to clear its content (even if no data is sent out). .com .com .com .com 4 .com u datasheet
STW5095 3 functional description 19/69 3.16 headset plug-in and push-button detection STW5095 can detect the plug-in of a microphone connector and the press/release event of a call/answer push-button. an application example can be found below, while specifications can be found in section 9.4 on page 54 . 3.17 microphone biasing circuit the microphone biasing circuit can drive mono or stereo microphones and can switch them off when not needed in order to save the current used by the microphone biasing network. two bits control the behavior of the microphone bias circuit: mbias in cr17 enables the circuit (fixed voltage at mbias pin), while bit mbiaspd in cr17 affects the behavior of mbias pin when the function is not enabled. in particular when mbiaspd=1 the mbias pin is pulled down, otherwise it is left in tristate mode. the specification for the microphone biasing circuit can be found in section 9.6 on page 55 , and an application note is shown in section 17 on page 66 . figure 3. plug-in and push-butt on detection application note call/answer button 10 f 1.5k ? vcca 3k ? 200nf aux1l aux1r capmic hdet 200nf STW5095 generic connector from driver .com .com .com .com 4 .com u datasheet
4 control registers STW5095 20/69 4 control registers 4.1 summary cr# (hex) descriptiond7d6d5 d4 d3d2d1d0def. cr0 (00h) supply & power control #1 powerup enana enamck enosc enpll enhsd a24v d12v 0000 0000 cr1 (01h) power control #2 enadcl enadcr endacl endacr enmicl enmicr enlinl enlinr 0000 0000 cr2 (02h) power control #3 enlol enlor enhpl enhpr enhpvcm enls enmixl enmixr 0000 0000 cr3 (03h) mic gain left micla(2:0) miclg(4:0) 0000 0000 cr4 (04h) mic gain right micra(2:0) micrg(4:0) 0000 0000 cr5 (05h) line in gain left x x x linlg(4:0) 0000 1001 cr6 (06h) line in gain right x x x linrg(4:0) 0000 1001 cr7 (07h) lo gain & ls gain x log(2:0) lsg(3:0) 0000 0011 cr8 (08h) hpl gain x x x hplg(4:0) 0000 0011 cr9 (09h) hpr gain x x x hprg(4:0) 0000 0011 cr10 (0ah) dac digital gain left x x daclg(5:0) 0000 0000 cr11 (0bh) dac digital gain right x x dacrg(5:0) 0000 0000 cr12 (0ch) adc digital gain left x x adclg(5:0) 0000 1000 cr13 (0dh) adc digital gain right x x adcrg(5:0) 0000 1000 cr14 (0eh) bass/treble/de-emphasis dync treble(2:0) bass(3:0) 0000 0000 cr15 (0fh) da to ad mixing gain x x x da2adg(4:0) 0000 0000 cr16 (10h) ad to da mix/sidetone gain x x ad2dag(5:0) 0000 0000 cr17 (11h) mixer switches & mic bias mbias mbiaspd admic adlin mixmic mixlin mixdac miclo 0000 0000 cr18 (12h) input switches x in2vcm linmute linsel(1:0) micmute micsel(1:0) 0010 0100 cr19 (13h) drivers control vcml(1:0) x mutelo mutehp lslim lssel(1:0) 0101 1000 cr20 (14h) daock frequency ls byte daockf(7:0) 0000 0000 cr21 (15h) daock frequency ms byte daockf(15:8) 0000 0000 cr22 (16h) da clock generator control x x damast damastgen endaock daock512 dapcmf(1:0) 0000 0000 cr23 (17h) adock frequency ls byte adockf(7:0) 0000 0000 cr24 (18h) adock frequency ms byte adockf(15:8) 0000 0000 cr25 (19h) ad clock generator con- trol x x admast admastgen enadock adock512 adpcmf(1:0) 0000 0000 cr26 (1ah) dac data if control x daform(2:0) daspim dawl(2:0) 0000 0000 cr27 (1bh) adc data if control adrtol adform2:0) adspim adwl(2:0) 0000 0000 cr28 (1ch) dac&adc data if control amckinv dackp dasyncp damono adckp adsyncp admono adhiz 0000 0000 cr29 (1dh) digital filters control x davoice da96k rxnh advoice ad96k adnh txnh 0000 0000 cr30 (1eh) soft reset & amck range swres x x x amcksin ckrange(2:0) 0000 0000 cr31 (1fh) interrupt mask vlshen pushben hsdeten vlshmsk pushbmsk hsdetmsk ovfmsk pormsk 0000 0000 cr32 (20h) interrupt status vlsh pushb hsdet vlshev pushbev hsdetev ovfev porev 0000 0000 cr33 (21h) misc. control x x spiohiz spiosel(1:0) irqcmos ovfda ovfad 0000 0000 cr34 (22h) agc attack/decay coeff. agcatt(3:0) agcdec(3:0) 0000 0000 cr35 (23h) agc control x enagclin enagcmic agcrange agclev(3:0) 0000 0000 cr36 (24h) reserved x x x x x x x x 0000 0000 note: x reserved, write zero .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 21/69 4.2 supply and power control cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr0 (00h) supply & power control #1 powerup enana enamck enosc enpll enhsd a24v d12v 0000 0000 cr1 (01h) power control #2 enadcl enadcr endacl endacr enmicl enmicr enlinl enlinr 0000 0000 cr2 (02h) power control #3 enlol enlor enhpl enhpr enhpvcm enls enmixl enmixr 0000 0000 bits name val. cr0 description def. 7powerup 1 0 all the enabled analog and digital blocks are in power up all the device is in power down 0 6 enana 1 0 the analog blocks can be enabled all the analog blocks are in power down 0 5enamck 1 0 amck clock input pin is enabled amck clock input pin is disabled 0 4enosc 1 0 the internal oscillator is enabled. the analog blocks use oscillator clock the internal oscillator is in power down 0 3enpll 1 0 the pll is enabled the pll is in power down 0 2 enhsd 1 0 the headset plug-in detector is enabled the headset plug-in detector is disabled 0 1a24v 1 0 analog supply pins voltage range is 2.4v 4 control registers STW5095 22/69 bits name value cr1 description def. 7 enadcl 1 0 the left channel a/d converter is enabled the left channel a/d converter is in power down 0 6 enadcr 1 0 the right channel a/d converter is enabled the right channel a/d converter is in power down 0 5endacl 1 0 the left channel d/a converter is enabled the left channel d/a converter is in power down 0 4endacr 1 0 the right channel d/a converter is enabled the right channel d/a converter is in power down 0 3enmicl 1 0 the left channel microphone preamplifier is enabled the left channel microphone preamplifier is in power down 0 2enmicr 1 0 the right channel microphone preamplifier is enabled the right channel microphone preamplifier is in power down 0 1enlinl 1 0 the left channel line-in preamplifier is enabled the left channel line-in preamplifier is in power down 0 0enlinr 1 0 the right channel line-in preamplifier is enabled the right channel line-in preamplifier is in power down 0 bit # name value cr2 description def. 7enlol 1 0 the left channel line out driver is enabled the left channel line out driver is in power down (default) 0 6enlor 1 0 the right channel line out driver is enabled the right channel line out driver is in power down (default) 0 5 enhpl 1 0 the left channel headphones driver is enabled the left channel headphones driver is in power down (default) 0 4 enhpr 1 0 the right channel headphones driver is enabled the right channel headphones driver is in power down (default) 0 3 enhpvcm 1 0 the headphones reference voltage generator is enabled the headphones reference voltage generator is in power down (def) 0 2enls 1 0 the 8 ? loudspeaker amplifier is enabled the 8 ? loudspeaker amplifier is in power down (default) 0 1enmixl 1 0 the left channel analog output mixer is enabled the left channel analog output mixer is in power down (default) 0 0enmixr 1 0 the right channel analog output mixer is enabled the right channel analog output mixer is in power down (default) 0 .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 23/69 4.3 gains cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr3 (03h) mic gain left micla(2:0) miclg(4:0) 0000 0000 cr4 (04h) mic gain right micra(2:0) micrg(4:0) 0000 0000 cr5 (05h) line in gain left x x x linlg(4:0) 0000 1001 cr6 (06h) line in gain right x x x linrg(4:0) 0000 1001 cr7 (07h) lo gain & ls gain x log(2:0) lsg(3:0) 0000 0011 cr8 (08h) hpl gain x x x hplg(4:0) 0000 0011 cr9 (09h) hpr gain x x x hprg(4:0) 0000 0011 cr10 (0ah) dac digital gain left x x daclg(5:0) 0000 0000 cr11 (0bh) dac digital gain right x x dacrg(5:0) 0000 0000 cr12 (0ch) adc digital gain left x x adclg(5:0) 0000 1000 cr13 (0dh) adc digital gain right x x adcrg(5:0) 0000 1000 bits name cr3 name cr4 value cr3 and cr4 description def. 7-5 micla(2:0) micra(2:0) 000 001 010 ... 110 111 left (cr3) and right (cr4) channels microphone attenuation 0.0 db gain (default) -1.5 db gain -3.0 db gain ...step 1.5 db -9.0 db gain -12.0 db gain 000 4-0 miclg(4:0) micrg(4:0) 00000 00001 00010 ... 11010 left (cr3) and right (cr4) channels microphone gain 0.0 db gain (default) 1.5 db gain 3.0 db gain ...step 1.5 db 39.0 db gain 00000 bits name cr5 name cr6 value cr5 and cr6 description def. 4-0 linlg(4:0) linrg(4:0) 00000 00001 00010 ... 01001 ... 10011 left (cr5) and right (cr6) channels line in gain 18.0 db gain 16.0 db gain 14.0 db gain ...step 2.0 db 0.0 db gain (default) ...step 2.0 db -20.0 db gain 01001 .com .com .com .com 4 .com u datasheet
4 control registers STW5095 24/69 bits name value cr7 description def. 6-4 log(2:0) 000 001 010 ... 110 left and right channel line out drivers gain 000 3-0 lsg(3:0) 0000 0001 0010 0011 ... 1111 8 ? loudspeaker gain 6.0 db gain 4.0 db gain 2.0 db gain 0.0 db gain (default) ...step 2.0 db -24.0 db gain 0011 bits name cr8 name cr9 value cr8 and cr9 description def. 4-0 hplg(4:0) hprg(4:0) 00000 00001 00010 00011 ... 10100 left (cr8) and right (cr9) channels headphones driver gain 0.0 db gain -2.0 db gain -4.0 db gain -6.0 db gain (default) ...step 2.0 db -40.0 db gain 00011 gain to differential output equivalent single-ended gain -18.0 db gain (default) -24.0 db gain (default) -15.0 db gain -21.0 db gain -12.0 db gain -18.0 db gain ...step 3 db ...step 3 db 00 db gain -6.0 db gain .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 25/69 bits name cr10 name cr11 value cr10 and cr11 description def. 5-0 daclg(5:0) dacrg(5:0) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 left (cr10) and right (cr11) channels dac digital gain 0.0 db gain (default) -1.0 db gain -2.0 db gain -3.0 db gain -4.0 db gain -5.0 db gain -6.0 db gain -7.0 db gain -8.0 db gain -9.0 db gain -10.0 db gain -11.0 db gain -12.0 db gain -13.0 db gain -14.0 db gain -15.0 db gain -16.0 db gain -17.0 db gain -18.0 db gain -20.0 db gain -22.0 db gain -24.0 db gain -26.0 db gain -28.0 db gain -30.0 db gain -32.0 db gain -34.0 db gain -36.0 db gain -38.0 db gain -41.0 db gain -44.0 db gain -47.0 db gain -50.0 db gain -53.0 db gain -56.0 db gain -59.0 db gain -65.0 db gain - db gain 000000 .com .com .com .com 4 .com u datasheet
4 control registers STW5095 26/69 bits name cr12 name cr13 value cr12 and cr13 description def. 5-0 adclg(5:0) acdrg(5:0) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 left (cr12) and right (cr13) channels adc digital gain 8.0 db gain 7.0 db gain 6.0 db gain 5.0 db gain 4.0 db gain 3.0 db gain 2.0 db gain 1.0 db gain 0.0 db gain (default) -1.0 db gain -2.0 db gain -3.0 db gain -4.0 db gain -5.0 db gain -6.0 db gain -7.0 db gain -8.0 db gain -9.0 db gain -10.0 db gain -11.0 db gain -12.0 db gain -14.0 db gain -16.0 db gain -18.0 db gain -20.0 db gain -22.0 db gain -24.0 db gain -26.0 db gain -28.0 db gain -30.0 db gain -33.0 db gain -36.0 db gain -39.0 db gain -42.0 db gain -45.0 db gain -48.0 db gain -51.0 db gain -57.0 db gain - db gain 001000 .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 27/69 4.4 dsp control cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr14 (0eh) bass/treble/de-emphasis dync treble(2:0) bass(3:0) 0000 0000 cr15 (0fh) da to ad mixing gain x x x da2adg(4:0) 0000 0000 cr16 (10h) ad to da mix/sidetone gain x x ad2dag(5:0) 0000 0000 bits name value cr14 description def. 7dync 1 0 audio dynamic compression in d/a path is enabled audio dynamic compression in d/a path is disabled 0 6-4 treble(2:0) 011 010 001 000 111 110 101 100 treble control in d/a path +6.0 db treble gain +4.0 db treble gain +2.0 db treble gain 0.0 db treble gain -2.0 db treble gain -4.0 db treble gain -6.0 db treble gain de-emphasis filter enabled 000 3-0 bass(3:0) 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 bass control in d/a path +12.5 db bass gain +10.0 db bass gain +7.5 db bass gain +5.0 db bass gain +2.5 db bass gain 0.0 db bass gain -2.5 db bass gain -5.0 db bass gain -7.5 db bass gain -10.0 db bass gain -12.5 db bass gain 0000 .com .com .com .com 4 .com u datasheet
4 control registers STW5095 28/69 bits name value cr15 description def. 4-0 da2adg(4:0)* 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 da to ad mixing (audio filter in d/a and a/d path selected) da to ad mixing disabled (default) +2.0 db gain 0.0 db gain -2.0 db gain -4.0 db gain -6.0 db gain -8.0 db gain -10.0 db gain -12.0 db gain -14.0 db gain -16.0 db gain -18.0 db gain -20.0 db gain -22.0 db gain -24.0 db gain -26.0 db gain -28.0 db gain -30.0 db gain -32.0 db gain -34.0 db gain -36.0 db gain -38.0 db gain -40.0 db gain 00000 * when voice filter in d/a or a/d path is selected this function is disabled note: d/a to a/d mixing is performed at ad data rate, so if a/d and d/a rates are different then asynchronous sampling artifacts may occur. .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 29/69 bits name value cr16 description def. 5-0 ad2dag(5:0) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 ad to da mixing (sidetone) ad to da mixing disabled (default) -1.0 db gain -2.0 db gain -3.0 db gain -4.0 db gain -5.0 db gain -6.0 db gain -7.0 db gain -8.0 db gain -9.0 db gain -10.0 db gain -11.0 db gain -12.0 db gain -13.0 db gain -14.0 db gain -15.0 db gain -16.0 db gain -17.0 db gain -18.0 db gain -19.0 db gain -20.0 db gain -21.0 db gain -22.0 db gain -23.0 db gain -24.0 db gain -25.0 db gain -26.0 db gain -27.0 db gain -28.0 db gain -29.0 db gain -30.0 db gain -31.0 db gain -32.0 db gain -33.0 db gain -34.0 db gain -35.0 db gain -36.0 db gain -37.0 db gain -38.0 db gain -39.0 db gain -40.0 db gain -41.0 db gain -42.0 db gain 000000 .com .com .com .com 4 .com u datasheet
4 control registers STW5095 30/69 4.5 analog functions cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr17 (11h) mixer switches & mic bias mbias mbiaspd admic adlin mixmic mixlin mixdac miclo 0000 0000 cr18 (12h) input switches x in2vcm linmute linsel(1:0) micmute micsel(1:0) 0010 0100 cr19 (13h) drivers control vcml(1:0) x mutelo mutehp lslim lssel(1:0) 0101 1000 bits name value cr17 description def. 7 mbias 1 0 microphone bias enabled (2.1v typ at mbias pin) microphone bias disabled 0 6 mbiaspd 1 0 mbias pin is pulled down when microphone bias is disabled mbias pin is in high impedance state when microphone bias is disabled 0 5admic 1 0 microphone preamplifiers are connected to ad path microphone preamplifiers are not connected to ad path 0 4adlin 1 0 line in preamplifiers are connected to ad path line in preamplifiers are not connected to ad path 0 3mixmic 1 0 microphone preamplifiers are connected to mixers microphone preamplifiers are not connected to mixers 0 2mixlin 1 0 line in preamplifiers are connected to mixers line in preamplifiers are not connected to mixers 0 1mixdac 1 0 stereo dac path is connected to mixers stereo dac path is not connected to mixers 0 0miclo 1 0 microphone preamplifiers are connected to line out drivers mixers are connected to line out drivers 0 .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 31/69 bits name value cr18 description def. 6in2vcm 1 0 unused analog input pins are biased to common mode voltage unused analog input pins are in high impedance state 0 5linmute 1 0 line in preamplifiers are muted line in preamplifiers are not muted 1 4-3 linsel(1:0) 00 01 10 11 input pins connected to line in preamplifiers (if linmute=0) 00 2micmute 1 0 microphone preamplifiers are muted microphone preamplifiers are not muted 1 1-0 micsel(1:0) 00 01 10 11 input pins connected to microphone preamplifiers (if micmute=0) 00 bits name value cr19 description def. 7-6 vcml(1:0) 00 01 10 11 common mode voltage level for line out and headphones drivers 1.20 v 1.35 v (default) 1.50 v 1.65 v 01 4mutelo 1 0 line out drivers are muted line out drivers are not muted 1 3mutehp 1 0 headphones drivers (hp) are muted headphones drivers (hp) are not muted 1 2lslim 1 0 loudspeaker driver (ls) gain is limited when v ccls is above 4.2v typ loudspeaker driver (ls) gain is not limited 0 1-0 lssel(1:0) 00 linein (lineinl, lineinr) aux1 (aux1l, aux1r) aux2 (aux2lp-aux2ln, aux2rp-aux2rn) aux3 ( aux3l, aux3r) mic (miclp-micln, micrp-micrn) aux1 (aux1l, aux1r) aux2 (aux2lp-aux2ln, aux2rp-aux2rn) aux3 ( aux3l, aux3r) 00 01 10 11 mute loudspeaker driver (ls) is muted right right channel mixer only connected to loudspeaker driver left left channel mixer only connected to loudspeaker driver mono (left + right)/2 channel mixers connected to loudspeaker driver .com .com .com .com 4 .com u datasheet
4 control registers STW5095 32/69 4.6 digital audio interfaces master mode and clock generators cr# (hex) descriptiond7d6d5 d4 d3d2d1d0def. cr20 (14h) daock frequency ls byte daockf(7:0) 0000 0000 cr21 (15h) daock frequency ms byte daockf(15:8) 0000 0000 cr22 (16h) da clock generator control x x damast damastgen endaock daock512 dapcmf(1:0) 0000 0000 cr23 (17h) adock frequency ls byte adockf(7:0) 0000 0000 cr24 (18h) adock frequency ms byte adockf(15:8) 0000 0000 cr25 (19h) ad clock generator control x x admast admastgen enadock adock512 adpcmf(1:0) 0000 0000 bits name cr21-20 name cr24-23 value cr21-20 and cr24-23 description def. 15-0 daockf(15:0) adockf(15:0) k the following formulas can be used to obtain the value of k for the desired fs or ock respectively in the clock generator 0000h note: cr21-20 and cr24-23 are meaningful in master mode only. kfs () round 2 25 fs amck mckcoeff ? -------------------------------------------------------------- ?? ?? = kock () round 2 25 ock amck mckcoeff osr ? ? ----------------------------------------------------------------------------------- - ?? ?? = fs: data rate (da_sync or ad_sync frequency in master mode) ock: oversampled clock frequency (da_ock or ad_ock) amck: input master clock frequency mckcoeff: see cr30 for definition osr: see bit 2 in cr22 and cr25 .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 33/69 bits name cr22 (name cr25) value cr22 and cr25 description def. 5 damast (admast) 1 0 da (ad) audio interface is in master mode (low impedance output) da (ad) audio interface is in slave mode (high impedance input) 0 4 damastgen (admastgen) 1 0 da (ad) master generator is enabled da (ad) master generator is disabled 0 3 endaock (enadock) 1 0 da_ock (ad_ock) output clock is enabled da_ock (ad_ock) output clock is disabled 0 2 daock512 (adock512) 1 0 definition of da_osr (ad_osr) da_ock/da_sync (ad_ock/ad_sync) ratio in master mode is 512 da_ock/da_sync (ad_ock/ad_sync) ratio in master mode is 256 0 1-0 dapcmf(1:0) (adpcmf(1:0)) 00 00 01 10 11 11 da_ck/da_sync (ad_ck/ad_sync) ratio in pcm master mode - 16 when cr26 dawl=000 (cr27 adwl=000) - 32 when cr26 dawl 000 (cr27 adwl 000) -64 - 128 - 256 when cr22 daock512=0 (cr25 adock512=0) - 512 when cr22 daock512=1 (cr25 adock512=1) 00 .com .com .com .com 4 .com u datasheet
4 control registers STW5095 34/69 4.7 digital audio interfaces cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr26 (1ah) dac data if control x daform(2:0) daspim dawl(2:0) 0000 0000 cr27 (1bh) adc data if control adrtol adform2:0) adspim adwl(2:0) 0000 0000 cr28 (1ch) dac&adc data if control amckinv dackp dasyncp damono adckp adsyncp admono adhiz 0000 0000 bits name value cr26 description def. 6-4 daform(2:0) 000 001 010 011 100 111 da audio interface format selection delayed format (i 2 s compatible) left aligned format right aligned format dsp format spi format pcm format (uses left channel) 000 3 daspim 1 0 da interface in spi mode receives one word for both channels da interface in spi mode receives two words (alternated, left channel first) 0 2-0 dawl(2:0) 000 001 010 011 100 da interface word length 16 bit 18 bit 20 bit 24 bit 32 bit 000 bits name value cr27 description def. 7adrtol 1 0 ad right channel sent to pcm i/f (must set enadcr=0 in cr1) normal operation 0 6-4 adform(2:0) 000 001 010 011 100 111 ad audio interface format selection delayed format (i 2 s compatible) left aligned format right aligned format dsp format spi format pcm format (sends out left channel) 000 3 adspim 1 0 ad interface in spi mode sends one channel (left) ad interface in spi mode sends two channels (alternated, left first) 0 2-0 adwl(2:0) 000 001 010 011 100 ad interface word length 16 bit 18 bit 20 bit 24 bit 32 bit 000 .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 35/69 bits name value cr28 description def. 7amckinv 1 0 amck is inverted amck is not inverted 0 6dackp 1 0 da bit clock pin (da_ck) polarity is inverted da bit clock pin (da_ck) polarity is not inverted 0 5 dasyncp 1 0 dsp and pcm formats in da interface non delayed format delayed format 0 1 0 delayed, left-aligned, right-aligned and spi formats in da interface da sync pin (da_sync) polarity is inverted da sync pin (da_sync) polarity is not inverted 4damono 1 0 mono mode: (l+r)/2 from audio interface is used on both dac channels stereo mode 0 3 adckp 1 0 ad bit clock pin (ad_ck) polarity is inverted ad bit clock pin (ad_ck) polarity is not inverted 0 2 adsyncp 1 0 dsp and pcm formats in ad interface non delayed format delayed format 0 1 0 delayed, left-aligned, right-aligned and spi formats in ad interface da sync pin (da_sync) polarity is inverted da sync pin (da_sync) polarity is not inverted 1admono 1 0 mono mode: (l+r)/2 from adc is sent to both channels in the audio interface stereo mode 0 0 adhiz 1 0 ad data pin (ad_data) is in high impedance state when no data is available ad data pin (ad_data) is forced to 0 when no data is available 0 .com .com .com .com 4 .com u datasheet
4 control registers STW5095 36/69 4.8 digital filters, software reset and master clock control cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr29 (1dh) digital filters control x davoice da96k rxnh advoice ad96k adnh txnh 0000 0000 cr30 (1eh) soft reset & amck range swres x x x amcksin ckrange(2:0) 0000 0000 bits name value cr29 description def. 6davoice 1 0 da path voice rx filter is enabled (single channel, left used) da path audio filters are enabled 0 5da96k 1 0 da path data rate is in the range 88 khz to 96 khz da path data rate is in the range 8 khz to 48 khz 0 4rxnh 1 0 da path high pass voice rx filter is disabled da path high pass voice rx filter is enabled (300hz @ 8khz rate) 0 3advoice 1 0 ad path voice tx filter is enabled (single channel, left used) ad path audio filters are enabled 0 2ad96k 1 0 ad path data rate is in the range 88 khz to 96 khz ad path data rate is in the range 8 khz to 48 khz 0 1 adnh 1 0 ad path audio dc filter is disabled ad path audio dc filter is enabled 0 0txnh 1 0 ad path high pass voice tx filter is disabled ad path high pass voice tx filter is enabled (300hz @ 8khz rate) 0 bits name value cr30 description def. 7swres 1 0 software reset: all registers content is reset to the default value control register content is left unchanged 0 3 amcksin 1 0 signal at amck pin is a sinusoid signal at amck pin is a square wave 0 2-0 ckrange(2:0) 000 001 010 011 100 101 000 amck range mckcoeff 4.0 mhz to 6.0 mhz 8.0 6.0 mhz to 8.0 mhz 6.0 8.0 mhz to 12.0 mhz 4.0 12.0 mhz to 16.0 mhz 3.0 16.0 mhz to 24.0 mhz 2.0 24.0 mhz to 32.0 mhz 1.5 .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 37/69 4.9 interrupt control and control interface spi out mode note: value at irq pin is: cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr31 (1fh) interrupt mask vlshen pushben hsdeten vlshmsk pushbmsk hsdetmsk ovfmsk pormsk 0000 0000 cr32 (20h) interrupt status vlsh pushb hsdet vlshev pushbev hsdetev ovfev porev 0000 0000 cr33 (21h) misc. control x x spiohiz spiosel(1:0) irqcmos ovfda ovfad 0000 0000 bits name value cr31 description def. 7vlshen 1 0 vlsh status can be seen at irq output vlsh status is masked 0 6 pushben 1 0 pushb status can be seen at irq output pushb status is masked 0 5 hsdeten 1 0 hsdet status can be seen at irq output hsdet status is masked 0 4vlshmsk 1 0 vlsh event can be seen at irq output vlsh event is masked 0 3 pushbmsk 1 0 pushb event can be seen at irq output pushb event is masked 0 2 hsdetmsk 1 0 hsdet event can be seen at irq output hsdet event is masked 0 1ovfmsk 1 0 ovf event can be seen at irq output ovf event is masked 0 0pormsk 1 0 por event can be seen at irq output por event is masked 0 irq (1 or z) when (cr31 & cr32) = 00 hex 0 when (cr31 & cr32) 00 hex ? ? ? = .com .com .com .com 4 .com u datasheet
4 control registers STW5095 38/69 bits name read only cr32 description def. 7vlsh* 1 0 v ccls is above 4.2 v v ccls is below 4.0 v 0 6 pushb* 1 0 headset button is pressed headset button is released 0 5 hsdet* 1 0 headset connector is inserted headset connector is not inserted 0 4vlshev 1 0 vlsh bit has changed vlsh bit has not changed 0 3 pushbev 1 0 headset button status has changed headset button status has not changed 0 2 hsdetev 1 0 headset connector status has changed headset connector status has not changed 0 1 ovfev 1 0 an audio data overflow has occurred in dsp no audio data overflow has occurred in dsp 0 0porev 1 0 device was reset by power-on-reset device was not reset by power-on-reset 0 note: content of bits 4 to 0 in cr32 is cleared after reading, while it is left unchanged if accessed for writing. *bits 7 to 5 represent the status when the contro l register is read, not when the event occurred. bits name val. cr33 description def. 5 spiohiz 1 0 spi control interface out pin is set to high impedance state when inactive spi control interface out pin is set to zero when inactive 0 4-3 spiosel(1:0) 00 01 10 11 out pin selection for spi control interface no output. control registers cannot be read in spi mode spi output sent to irq pin spi output sent to da_ock pin spi output sent to ad_ock pin 00 2 irqcmos 1 0 irq interrupt request pin is set to cmos (active low) irq interrupt request pin is set to pull down 0 1ovfda 1 0 an overflow (saturation) occurred in da path no overflow occurred in da channel 0 0 ovfad 1 0 an overflow (saturation) occurred in ad path no overflow occurred in ad channel 0 note: content of bits 1 to 0 in cr33 is cleared after reading, while it is left unchanged if accessed for writing. .com .com .com .com 4 .com u datasheet
STW5095 4 control registers 39/69 4.10 agc cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr34 (22h) agc attack/decay coeff. agcatt(3:0) agcdec(3:0) 0000 0000 cr35 (23h) agc control x enagclin enagcmic agcrange agclev(3:0) 0000 0000 bits name value cr34 description def. 7-4 agcatt(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 agc attack time constant; fs=ad data rate 0000 audio filter in ad path 4096 / fs 2048 / fs 1365 / fs 1024 / fs 683 / fs 512 / fs 341 / fs 256 / fs 171 / fs 128 / fs 85 / fs 64 / fs 43 / fs 32 / fs voice filter in ad path 8192 / fs 4096 / fs 2731 / fs 2048 / fs 1365 / fs 1024 / fs 683 / fs 512 / fs 341 / fs 256 / fs 171 / fs 128 / fs 85 / fs 64 / fs 3-0 agcdec(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 agc decay time constant; fs=ad data rate 0000 audio filter in ad path 65536 / fs 32768 / fs 21845 / fs 16384 / fs 10923 / fs 8192 / fs 5461 / fs 4096 / fs 2731 / fs 2048 / fs 1365 / fs 1024 / fs 683 / fs 512 / fs 341 / fs 256 / fs voice filter in ad path 131072 / fs 65536 / fs 43691 / fs 32768 / fs 21845 / fs 16384 / fs 10923 / fs 8192 / fs 5461 / fs 4096 / fs 2731 / fs 2048 / fs 1365 / fs 1024 / fs 683 / fs 512 / fs .com .com .com .com 4 .com u datasheet
4 control registers STW5095 40/69 bits name value cr35 description def. 6enagclin 1 0 agc control on ad path acts on line in gain agc control on ad path does not act on line in gain 0 5enagcmic 1 0 agc control on ad path acts on mic gain agc control on ad path does not act on mic gain 0 4 agcrange 1 0 agc action range is -21.0 db to +21.0 db agc action range is -10.5 db to +10.5 db 0 3-0 agclev(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 agc requested output level -30.0 db gain -30.0 db gain -27.0 db gain -24.0 db gain -21.0 db gain -18.0 db gain -15.0 db gain -12.0 db gain -9.0 db gain -6.0 db gain 0000 .com .com .com .com 4 .com u datasheet
STW5095 5 control interface and master clock 41/69 5 control interface and master clock 5.1 control interface i 2 c mode note: cmod pin tied to gnd figure 4. control interface i 2 c format figure 5. control interface: i 2 c format timing write single byte start device address reg n address reg n data in ack ack ack stop write multi byte start device address reg n address reg n data in ack ack ack stop reg n+m data in ack m+1 data bytes current addr start device address current reg data out ack no ack stop read single byte current addr start device address current reg data out ack no ack stop read multi byte curr reg+m data out ack ack ack m+1 data bytes start device address reg n address ack ack start device address reg n data out ack no ack stop random addr read single byte random addr read multi byte start device address reg n address ack ack start device address no ack stop reg n+m data out ack ack m+1 data bytes reg n data out ack 001101as 1 001101as 1 001101as0 001101as0 001101as1 001101as1 001101as0 001101as0 (sto) t su (sta) t su (sta) t hd (dat) t su t high t buf (dat) t hd t f t r t low (sta) t hd p s p s r p=stop s = start sr = start repeated sda sclk .com .com .com .com 4 .com u datasheet
5 control interface and master clock STW5095 42/69 control interface timing with i2c format 5.2 control interface spi mode symbol parameter test condition min. typ. max. unit f scl clock frequency 400 khz t high clock pulse width high 600 ns t low clock pulse width low 1300 ns t r sda and sclk rise time 1000 ns t f sda and sclk fall time 300 ns t hd:sta start condition hold time 600 ns t su:sta start condition setup time 600 ns t hd:dat data input hold time 0 ns t su:dat data input setup time 250 ns t su:sto stop condition setup time 600 ns t buf bus free time 1300 ns figure 6. control interface spi format (1) 1. cmod pin tied to v ccio ; sdo pin position selected with bits spiosel in cr33. a6 a5 8 bit address a4 a3 a2 a1 a0 w/r d7 d6 d5 d4 d3 d2 d1 d0 8 bit data sdin d7 d6 d5 d4 d3 d2 d1 d0 8 bit data sdo sclk csb spiohiz=1 .com .com .com .com 4 .com u datasheet
STW5095 5 control interface and master clock 43/69 control interface signal timing with spi format figure 7. control interface: spi format timing symbol parameter test condition min. typ. max. unit t hics csb pulse width high 80 ns t scsr setup time csb rising edge to sclk rising edge 20 ns t scsf setup time csb falling edge to sclk rising edge 20 ns t hcs hold time csb rising edge from sclk rising edge 20 ns t sdi setup time sdin to sclk rising edge 20 ns t hdi hold time sdin from sclk rising edge 20 ns t ddof sdo first delay time from sclk falling edge 30 ns t ddo sdo delay time from sclk falling edge 20 ns t ddol sdo delay time from csb rising edge 30 ns t psck period of sck 100 ns t hsck sck pulse width high measured from v ih to v ih 40 ns t lsck sck pulse width low measured from v il to v il 40 ns t ddo t ddol t ddof spiohiz=0 spiohiz=1 t scsf t hsck t lsck t sdi t hdi t scsr t hics sdin sdo sclk csb 15 8 0 w/r d7 d7 d0 d0 t psck t hcs .com .com .com .com 4 .com u datasheet
5 control interface and master clock STW5095 44/69 5.3 master clock timing amck timing symbol parameter amck range min. typ. max. unit t ckdc amck d uty cycle 4 mhz -8 mhz 8 mhz -32 m hz 45 40 55 60 % % .com .com .com .com 4 .com u datasheet
STW5095 6 audio interfaces 45/69 6 audio interfaces figure 8. audio interfaces formats: delayed, left and right justified 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 ad_ck/da_ck 1 ad_ck/da_ck n-bit word left data i2s format (delayed) with default polarity settings, adhiz=0 left justified format with default polarity settings, adhiz=0 n-bit word left data n-bit word right data n-bit word right data 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb n-bit word left data n-bit word left data n-bit word right data n-bit word right data 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb n-bit word left data right justified format with default polarity settings n-bit word left data n-bit word right data n-bit word right data 32 ad_ck/da_ck 32 ad_ck/da_ck da_sync/ ad_sync da_data ad_data da_ck/ ad_ck da_sync/ ad_sync da_data ad_data da_ck/ ad_ck da_sync/ ad_sync da_data ad_data da_ck/ ad_ck .com .com .com .com 4 .com u datasheet
6 audio interfaces STW5095 46/69 figure 9. audio interfaces formats: dsp, spi and pcm da_sync/ 1 2 n-1 n msb lsb ad_sync 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb n-bit word left data dsp format delayed and non-delayed (default ad_ck/da_ck polarity, adhiz=0) spi format (slave only) (default ad_ck/da_ck polarity, adhiz=1 - stereo or mono) n-bit word left data n-bit word right data n-bit word right data 1 2 n-1 n msb lsb 1 2 msb n-bit word left/mono data n-bit word right/mono data pcm format (default ad_ck/da_ck polarity, adhiz=1) 3 3 1 2 n-1 n msb lsb 1 2 msb n-bit word left/mono data n-bit word right/mono data 3 3 1 2 n-1 n msb lsb n-bit word mono data 3 1 2 n-1 msb lsb n-bit word mono data 3 high impedance 1 msb 1 msb x high impedance x syncp=0 syncp=1 { da_data ad_data da_ck/ ad_ck da_sync/ ad_sync da_data ad_data da_ck/ ad_ck da_sync/ ad_sync syncp=0 syncp=1 { da_data ad_data da_ck/ ad_ck n .com .com .com .com 4 .com u datasheet
STW5095 6 audio interfaces 47/69 figure 10. audio interface timings: master mode figure 11. audio interface timing: slave mode adhiz=0 adhiz=0 adhiz=1 adhiz=1 adhiz=0 adhiz=1 adhiz=0 adhiz=1 t dsy t sdda t hdda t dad ckp=0 ckp=1 t dad t dadz da_sync/ ad_sync da_ck/ ad_ck da_data { t dad pcm format only ad_data ad_data all other formats adhiz=0 adhiz=0 adhiz=1 adhiz=1 adhiz=0 adhiz=1 adhiz=0 t dadst t hck t lck t pck t ssy da_sync/ t sdda t hdda t hsy ad_sync t dad ckp=0 ckp=1 t dadz da_ck/ ad_ck da_data { t dad t dad pcm format ad_data ad_data all other formats adhiz=1 .com .com .com .com 4 .com u datasheet
6 audio interfaces STW5095 48/69 audio interface signals timing symbol parameter test condition min. typ. max. unit t dsy delay of ad_sync/ da_sync edge from ad_ck/da_ck active edge master mode 10 ns t sdda setup time da_data to da_ck active edge 10 ns t hdda hold time da_data from da_ck active edge 10 ns t dad delay of ad_data edge from ad_ck active edge 30 ns t dadst delay of the first ad_data edge from ad_sync active edge ad_sync active edge comes after ad_ck active edge 30 ns t dadz delay of ad_data high impedance from ad_sync inactive edge pcm format 10 50 ns t ssy setup time ad_sync/ da_sync to ad_ck/ da_ck active edge slave mode 20 ns t hsy hold time ad_sync/ da_sync from ad_ck/ da_ck active edge slave mode 20 ns t pck period of ad_ck/da_ck slave mode 100 ns t hck ad_ck/da_ck pulse width high measured from v ih to v ih 40 ns t lck ad_ck/da_ck pulse width low measured from v il to v il 40 ns .com .com .com .com 4 .com u datasheet
STW5095 7 timing specifications 49/69 7 timing specifications unless otherwise specified, v ccio =1.71v to 2.7v,t amb = -30c to 85c, max capacitive load 20 pf; typical characteristics are specified at v ccio = 2.4 v, t amb = 25 c; all signals are referenced to gnd, see note below figure for timing definitions. note: a signal is valid if it is above v ih or below v il and invalid if it is between v il and v ih . for the purpose of this specification the following conditions apply (see figure 12 above): a) all input signal are defined as: v il =0.2 ? v ccio , v ih =0.8 ? v ccio , t r < 10ns, t f < 10ns. b) delay times are measured from the inputs signal valid to the output signal valid. c) setup times are measured from the data input valid to the clock input invalid. d) hold times are measured from the clock signal valid to the data input invalid. note: all timing specifications subject to change. figure 12. a.c. testing input-output waveform ac testing: inputs are driven at 0.8 ? v ccio for a logic ?1? and 0.2 ? v ccio for a logic ?0?. timing measurements are made at 0.7 ? v ccio for a logic ?1? and 0.3 ? v ccio for a logic ?0?. test points 0.7 ? v ccio 0.3 ? v ccio 0.7 ? v ccio 0.3 ? v ccio 0.8 ? v ccio 0.2 ? v ccio input ? output .com .com .com .com 4 .com u datasheet
8 operative ranges STW5095 50/69 8 operative ranges 8.1 absolute maximum ratings 8.2 operative supply voltage parameter value unit v cc or v ccio to gnd -0.5 to 3.6 v v cca or v ccp to gnd -0.5 to 5 v v ccls to gnd -0.5 to 7 v voltage at analog inputs (v cca 3.3v) gnd-0.5 to v cca +0.5 v maximum power delivered to the load from lsp/n 500 mw peak current at hpr,hpl 100 ma current at v ccp , v ccls , gndp 350 ma current at any digital output 50 ma voltage at any digital input (v ccio 2.7v); limited at 50ma gnd-0.5 to v ccio +0.5 v storage temperature range -64 to 150 c operating temperature range (1) 1. in some operating conditions the temperature can be limited to 70 c. see loudspeaker driver description from section 3.9 for details. -30 to 85 c symbol parameter condition min. max. unit v cc digital supply 1.71 2.7 v v cca analog supply note: v cca v cc a24v=0 (bit 1 in cr0) a24v=1 (bit 1 in cr0) 2.7 2.4 3.3 2.7 v v v ccio digital i/o supply d12v=0 (bit 0 in cr0) d12v=1 (bit 0 in cr0) 1.71 1.2 v cc 1.8 v v v ccp stereo power drivers supply v cca 3.3 v v ccls mono power driver supply v cca 5.5 v v g single supply voltage range v cc = v cca = v ccio = v ccp = v ccls a24v=1 (bit 1 in cr0) 2.4 2.7 v .com .com .com .com 4 .com u datasheet
STW5095 8 operative ranges 51/69 8.3 power dissipation unless otherwise specified, v ccp =v ccls =v cca = 2.7v to 3.3v, v ccio =v cc = 1.71v to 2.7v, t amb = -30c to 85c, all analog outputs not loaded; typical characteristics are specified at v ccio =v cc = 1.8v, v ccp =v ccls =v cca =2.7v, t amb =25c. 8.4 typical power dissipation t amb = 25c; analog supply: v ccp =v ccls =v cca = 2.7v; digital supply:v ccio =v cc =1.8v full scale signal in every path, 20k ? load at analog outputs. no master clock symbol parameter test condition min. typ. max. unit poff power down dissipation no master clock amck=13mhz 0.2 2.9 w w pad stereo adc power 26.3 mw pda stereo dac power 22.6 mw pdaad stereo adc+dac power 44.0 mw paa stereo analog path power 13.8 mw n. function cr0-cr2 setting other settings supply current power 1 power down cr0=0x00 cr1=0x00 cr2=0x00 analog: digital: total: 0.02 a 0.20 a 0.05 w 0.36 w 0.41 w 2 stereo analog path (mic-lo) cr0=0xd0 cr1=0x0c cr2=0xc0 miclo=1 micsel=2 analog: digital: total: 4.3 ma 2.0 a 11.6 mw 0.0 mw 11.6 mw 3 stereo analog path (mic-mixer-lo) cr0=0xd0; cr1=0x0c; cr2=0xc3 mixmic=1 micsel=2 analog: digital: total: 5.4 ma 2.0 a 14.6 mw 0.0 mw 14.6 mw .com .com .com .com 4 .com u datasheet
8 operative ranges STW5095 52/69 master clock amck = 13 mhz n. function cr0-cr2 setting other settings supply current power 4 power down cr0=0x00 cr1=0x00 cr2=0x00 analog: digital: total: 0.02 a 2.20 a 0.05 w 3.96 w 4.01 w 5stereo adc cr0=0xe8 cr1=0xcc cr2=0x00 micsel=1 admic=1 analog: digital: total : 7.9 ma 2.8 ma 21.3 mw 5.0 mw 26.3 mw 6stereo dac cr0=0xe8 cr1=0x30 cr2=0x33 mixdac=1 analog: digital: total: 6.1 ma 3.8 ma 16.5 mw 6.8 mw 23.3 mw 7 stereo analog path (mic-lo) cr0=0xe8 cr1=0x0c cr2=0xc0 miclo=1 micsel=2 analog: digital: total: 4.8 ma 0.8 ma 13.0 mw 1.4 mw 13.8 mw 8 stereo adc stereo dac cr0=0xe8 cr1=0xfc cr2=0x33 micsel=2 admic=1 mixdac=1 analog: digital: total: 13.5 ma 5.8 ma 36.5 mw 10.4 mw 46.9 mw 9 stereo adc stereo dac stereo analog path cr0=0xe8 cr1=0xff cr2=0xf3 linsel=2; micsel=2 adlin=1;mixdac=1 miclo=1 analog: digital: total: 15.2 ma 5.8 ma 41.0 mw 10.4 mw 51.4 mw 10 voice tx+rx cr0=0xe8 cr1=0xa8 cr2=0x06 micsel=2; lsmode=2 admic=1 mixdac=1 advoice=1 davoice=1 v cca ,v ccp : v ccls : digital total: 6.8 ma 1.3 ma 2.5 ma 18.4 mw 5.5 mw 4.5 mw 28.4 mw .com .com .com .com 4 .com u datasheet
STW5095 9 electrical characteristics 53/69 9 electrical characteristics unless otherwise specified, v ccio = 1.71 v to 2.7 v, t amb = -30c to 85c; typical characteristic are specified at v ccio = 2.0 v, t amb = 25c; all signals are referenced to gnd. 9.1 digital interfaces note: see figure 12: a.c. testing input-output waveform on page 49 . 9.2 amck with sinusoidal input symbol parameter test condition min. typ. max. unit v il input low voltage all digital inputs dc ac 0.3 ? v ccio 0.2 ? v ccio v v v ih input high voltage all digital inputs, dc ac 0.7 ? v ccio 0.8 ? v ccio v v v ol output low voltage all digital outputs i l =10 a i l =2 a 0.1 0.4 v v v oh output high voltage all digital outputs i l =10 a i l =2 a v ccio -0.1 v ccio -0.4 v v i il input low current any digital input, gnd < v in < v il -1 1 a i ih input high current any digital input, v ih < v in < v ccio -1 1 a i oz output current in high impedance (tristate) tristate outputs -1 1 a symbol parameter test condition min. typ. max. unit c amck minimum external capacitance amcksin=1, see cr30 100 pf v amck amck sinusoidal voltage swing amcksin=1, see cr30 0.5 v ccio v pp .com .com .com .com 4 .com u datasheet
9 electrical characteristics STW5095 54/69 9.3 analog interfaces 9.4 headset plug-in and push-button detector symbol parameter test condition min. typ. max. unit i mic mic input leakage gnd< v mic < v cca -100 +100 a r mic mic input resistance 30 50 k ? r lin line in input resistance 30 k ? r lhp headphones (hp) drivers load resistance hpl, hpr to gndp or vcmhp 14.4 16/32 ? c lhp headphones (hp) drivers load capacitance hpl, hpr to gndp or vcmhp 50 50* pf nf r lls loudspeaker (ls) differential driver load resistance lsp to lsn 6.4 8 ? c lls loudspeaker (ls) differential driver load capacitance lsp to lsn 50 50* pf nf v offls differential offset voltage at lsp, lsn r l =50 ? -50 +50 mv r lol line out (ol) diff./single- ended driver load resistance olp/orp to oln/orn or olp/orp to gnd (decoupled) 1k ? c lol line out (ol) diff./single- ended driver load capacitance olp/orp to oln/orn or olp/orp to gnd tbd * with series resistor symbol parameter test condition min. typ. max. unit hd vl plug-in detected voltage at hdet v cca -1 v hd vh plug-in undetected voltage at hdet v cca -0.5 v hd h plug-in detector hysteresis 100 mv pb vl push-button pressed voltage at hdet 0.5 v pb vh push-button released voltage at hdet 1 v pb d push-button de-bounce time 15 50 ms .com .com .com .com 4 .com u datasheet
STW5095 9 electrical characteristics 55/69 9.5 microphone bias 9.6 power supply rejection ratio 9.7 ls gain limiter symbol parameter test condition min. typ. max. unit v mbias mbias output voltage 1.95 2.1 2.25 v i mbias mbias output current from mbias to ground 600 a r mbias mbias output load 3.5 k ? c mbias mbias output capacitance 150 pf psr mb4 psr mb20 mbias power supply rejection f<4khz f<20khz 60 50 db db symbol parameter test condition min. typ. max. unit psr l20 psr l200 psrr v ccls each output(lsp, lsn) f<20khz f<200khz 65 47 db db psr ph psr pos psr pod psrr v ccp headphones f<20khz line out single ended f<20khz line out differential f<20khz 65 tbd tbd db db db psr am psr al psrr v cca mic input f<20khz line in f<20khz 50 tbd db db symbol parameter test condition min. typ. max. unit vls limh high voltage at v ccls (vlsh=1) v ccls raising 4.2 v vls liml low voltage at v ccls (vlsh=0) v ccls falling 4.0 v vls limd v ccls hysteresis 200 mv note: see cr32 for vlsh definition. see loudspeaker driver description in section 3.9 for details. .com .com .com .com 4 .com u datasheet
10 analog input/output operative ranges STW5095 56/69 10 analog input/output operative ranges 10.1 analog levels reference full scale analog levels 10.2 microphone input levels absolute levels at pins connected to preamplifiers analog supply range: 2.7 v < v cca <3.3v symbol parameter test condition min. typ. max. unit 0dbfs level 2.7v < v cca < 3.3v 12 4 dbv pp v pp 0dbfs level low voltage mode 2.4v < v cca < 2.7v 10 3.18 dbv pp v pp symbol parameter test condition min. typ. max. unit overload level, single ended mic gain = 0 to 6db 707 2 -6 mv rms v pp dbfs overload level,single ended, versus mic gain mic gain > 6db ? ( mic_gain) dbfs overload level, differential mic gain = 0db 1.41 4 0 mv rms v pp dbfs overload level, differential, versus mic gain mic gain > 0db ? ( mic_gain) dbfs note: when 2.4 v < v cca < 2.7 v, voltage values are reduced by 2db. .com .com .com .com 4 .com u datasheet
STW5095 10 analog input/output operative ranges 57/69 10.3 line input levels absolute levels at pins connected to the line-in amplifiers analog supply range: 2.7 v < v cca <3.3 v 10.4 line output levels absolute levels at olp/oln, orp/orn analog supply range: 2.7 v < v cca <3.3v symbol parameter test condition min. typ. max. unit overload level, single ended line in gain from ? 20db to 6db 707 2 -6 mv rms v pp dbfs overload level (single ended) versus line in gain line in gain > 6db ? ( line_in_gain) dbfs overload level (differential) line in gain from ? 20db to 0db 1.41 4 0 mv rms v pp dbfs overload level (differential) versus line in gain line in gain > 0db ? ( line_in_gain) dbfs note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db symbol parameter test condition min. typ. max. unit output level, single ended 0 db gain full scale digital input 707 2 -6 mv rms v pp dbfs output level, differential 0 db gain full scale digital input 1.41 4 0 mv rms v pp dbfs note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db .com .com .com .com 4 .com u datasheet
10 analog input/output operative ranges STW5095 58/69 10.5 power output levels hp absolute levels at hpl - hpr analog supply range: 2.7 v < v cca <3.3v 10.6 power output levels ls absolute levels at lsp - lsn (differential) analog supply range: 2.7 v < v cca <3.3v symbol parameter test condition min. typ. max. unit output level -6db gain full scale digital input 707 2 -6 mv rms v pp dbfs max output power (1) 16 ? load v ccp > 3.2 v 40 mw note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db symbol parameter test condition min. typ. max. unit output level 0db gain full scale digital input 1.41 4 0 v rms v pp dbfs max output power (1) 1. in some operating conditions the maximum output power can be limited. see ? section 8.1: absolute maximum ratings ? and ?loudspeaker driver? description from section 3.9: analog output drivers for details. note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db 8 ? load v ccls > 4v 500 mw .com .com .com .com 4 .com u datasheet
STW5095 11 stereo audio adc specifications 59/69 11 stereo audio adc specifications typical measures at v cca =v ccp =v ccls =2.7v; v ccio =v cc =1.8 v; tamb=25 c;13 mhz amck symbol parameter test condition min. typ. max. unit adn resolution 20 bits addrm addrli dynamic range 20hz to 20khz, a-weighted measured at -60dbfs mic input, 21db gain line-in, 0db gain 87 89 91 93 db db adsna adsn signal to noise ratio max level at mic input, 21db gain a-weighted unweighted (20 hz to 20 khz) 90 86 db db input referred adc noise a-weighted mic input 0db gain mic input 21db gain mic input 39db gain line in input 0db gain line in input 18db gain 37 3.3 1.9 30 7.5 v v v v v adthd total harmonic distortion max level at mic input, 21db gain 0.001 0.003 % deviation from linear phase measurement bandwidth 20hz to 20khz, fs= 48khz. combined digital and analog filter characteristics 1deg adf pb passband combined digital and analog filter characteristics ad96k=0 00.45fskhz passband ripple combined digital and analog filter characteristics ad96k=0 0.2 db adf sb stopband combined digital and analog filter characteristics ad96k=0 0.55fs khz stopband attenuation measurement bandwidth up to 3.45fs. combined digital and analog filter characteristics, ad96k=0 60 db adt gd group delay audio filters, 96khz fs audio filters, 48khz fs audio filters, 8khz fs 0.11 0.4 2.6 ms ms ms interchannel isolation 90 db interchannel gain mismatch 0.2 db gain error 0.5 db note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db .com .com .com .com 4 .com u datasheet
12 stereo audio dac specifications STW5095 60/69 12 stereo audio dac specifications typical measures at v cca =v ccp =v ccls =2.7v; v ccio =v cc =1.8v; tamb=25 c;13mhz amck symbol parameter test condition min. typ. max. unit dan resolution 20 bits dadr dynamic range 20hz to 20khz, a-weighted. measured at -60dbfs differential line out single-ended line out hpl/hpr to gnd or vcmhp lsp-lsn 90 95 93 94 94 db db db db dasna dasn signal to noise ratio 2vpp output hpl, hpr gain set to -6db, 16 ? load a-weighted unweighted (20 hz to 20 khz) 94 90 db db dathdl total harmonic distortion worst case load 2v pp output hpl, hpr gain set to -6db, 16 ? load 0.02 0.04 % dathd total harmonic distortion 2v pp output, hpl, hpr gain set to -6db, 1k ? load 0.004 % deviation from linear phase measurement bandwidth 20hz to 20khz, fs= 48khz. combined digital and analog filter characteristics 1deg daf pb passband combined digital and analog filter characteristics, da96k=0 00.45fskhz passband ripple combined digital and analog filter characteristics, da96k=0 0.2 db daf sb stopband combined digital and analog filter characteristics, da96k=0 0.55fs khz stopband attenuation measurement bandwidth up to 3.45fs. combined digital and analog filter characteristics, da96k=0 50 db tsf transient suppression filter cut-off frequency 15 23 hz out of band noise measurement bandwidth 20 khz to 100 khz. zero input signal -85 dbr dat gd group delay audio filters, 96khz fs audio filters, 48khz fs audio filters, 8khz fs 0.09 0.4 2.6 ms ms ms interchannel isolation 2vpp output hpr, hpl unloaded hpr, hpl with 16 ? to vcmhp 100 60 db db .com .com .com .com 4 .com u datasheet
STW5095 13 ad to da mixing (sidetone) specifications 61/69 13 ad to da mixing (sidetone) specifications typical measures at v cca =v ccp =v ccls =2.7v; v ccio =v cc =1.8v; tamb=25 c;13mhz amck 14 stereo analog-only path specifications measured at differential line-out, enosc=1, no master clock. typical measures at v cca =v ccp =v ccls =2.7v; v ccio =v cc =1.8v; tamb=25 c interchannel gain mismatch 0.2 db gain error 0.5 db sut startup time from power up fs=48 khz line out hpl/r out 1 10 ms ms note: when 2.4 v < v cca < 2.7 v, values are reduced by 2 db symbol parameter test condition min. typ. max. unit stdel ad to da mixing (sidetone) delay valid for audio and voice filters 5 10 s symbol parameter test condition min. typ. max. unit aadrm aadrli dynamic range 20hz to 20khz, a-weighted. measured at -60dbfs mic input, 21db gain line-in, 0db gain 90 90 95 97 db db aasna aasn signal to noise ratio max level at line-in input, 0db gain, a-weighted unweighted (20 hz to 20 khz) 97 94 db db aathd total harmonic distortion 1khz @ 0dbfs mic input, 21db gain line-in input, 0db gain 0.003 0.004 0.01 0.02 % % note: when 2.4v 15 adc (tx) & dac (rx) specifications with voice filters selected STW5095 62/69 15 adc (tx) & dac (rx) specifications with voice filters selected typical measures at v cca =v ccp =v ccls =2.7v; v ccio =v cc =1.8v; tamb=25 c;13mhz amck symbol parameter test condition min. typ. max. unit txdr rxdr dynamic range 300hz to 3.4khz; 1khz @ -60dbfs tx path, mic input, 21db gain rx path, ls output, 0db gain 86 83 89 86 db db txsn rxsn signal to noise ratio 300hz to 3.4khz; 1khz @ 0dbfs tx path, mic input, 21db gain rx path, ls output, 0db gain 88 86 db db thd thd 1khz @ 0dbfs tx path, mic input, 21db gain rx path, ls output, 0db gain <0.001 0.005 % % txg tx gain mask f=60hz f=100hz f=200hz f=300hz f=400hz-3000hz f=3400hz f=4000h f=4600hzz f=8000hz -1.5 -0.5 -1.5 -30 -24 -6 0.5 0.5 0.0 -14 -35 -47 db db db db db db db db db rxg rx gain mask f=60hz f=100hz f=200hz f=300hz f=400hz-3000hz f=3400hz f=4000hz f=5000hz -1.5 -0.5 -1.5 -20 -12 -2 0.5 0.5 0.0 -14 -50 db db db db db db db db rx out of band noise measurement bandwidth 4khz to 100khz. zero input signal -85 dbr group delay tx path rx path 0.32 0.28 ms ms note: when 2.4v STW5095 16 typical performance plots 63/69 16 typical performance plots figure 13. bass treble control, de-emphasis filter figure 14. dynamic compressor transfer function figure 15. adc audio path measured filter response figure 16. adc in band a udio path measured filter response figure 17. dac digital audio filter characteristics figure 18. dac in band digital audio filter characteristics bass and treble gains are independently selectable in any combination. the de-emphasis filter (thick line, alternative to treble control) compensates for pre-emphasis used on some audio cds. gain error < 0.1db. filter characteristics at fs=44.1khz are plotted -15 -10 -5 0 5 10 15 100 1k 10k gain @ fs=44.1 khz [db] frequency [hz] audio signal transfer function when the dynamic compressor is active. -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 output amplitude [fs] input amplitude [fs] 48 khz sample rate. full adc path frequency response up to 100 khz. -80 -70 -60 -50 -40 -30 -20 -10 0 100 1k 10k 100k gain [db] frequency [hz] 48 khz sample rate. in band frequency response -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 5k 10k 15k 20k gain [db] frequency [hz] da96k=0; 48 khz sample rate frequency response up to 166khz (3.45 fs @ 48khz sampling rate) -80 -60 -40 -20 0 100 1k 10k 100k gain [db] frequency [hz] 48 khz sample rate in band frequency response -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 5k 10k 15k 20k gain [db] frequency [hz] .com .com .com .com 4 .com u datasheet
16 typical performance plots STW5095 64/69 figure 19. adc 96 khz audio path measured filter response figure 20. adc 96 khz audio in-band measured filter response figure 21. adc voice tx path measured filter response figure 22. adc voice tx path measured in- band filter response figure 23. dac voice (rx) digital filter characteristics figure 24. dac voice (rx) in-band digital filter characteristics the plot is extended down to 5 hz to show the high pass filter implemented in the adc 96 khz sample rate, 96 khz audio filter selected signal from mic input -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1k 10k 100k gain [db] frequency [hz] 96 khz sample rate, 96 khz audio filter selected signal from mic input. -5 -4 -3 -2 -1 0 1 0 5k 10k 15k 20k 25k 30k 35k 40k 45k gain [db] frequency [hz] 8 khz sample rate, tx voice filter selected. signal from mic input -70 -60 -50 -40 -30 -20 -10 0 100 1k 10k gain [db] frequency [hz] 8 khz sample rate, tx voice filter selected signal from mic input. -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 500 1k 1500 2k 2500 3k 3500 4k gain [db] frequency [hz] 8 khz sample rate, rx voice filter -70 -60 -50 -40 -30 -20 -10 0 100 1k 10k gain [db] frequency [hz] 8 khz sample rate, rx voice filter -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 500 1k 1500 2k 2500 3k 3500 4k gain [db] frequency [hz] .com .com .com .com 4 .com u datasheet
STW5095 16 typical performance plots 65/69 figure 25. adc path fft figure 26. adc s/n versus input-level figure 27. dac path fft figure 28. dac s/n versus input-level figure 29. analog path fft figure 30. analog path s/n versus input-level -120 -100 -80 -60 -40 -20 0 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k amplitude [dbfs] frequency [hz] 12 mhz master clock. differential input at mic preamplifier, 21 db gain. 48 khz sampling rate. both channels active 20 30 40 50 60 70 80 90 100 -60 -50 -40 -30 -20 -10 0 s/n [db] input level [dbfs] 12 mhz master clock differential input at line-in amplifier, 0 db gain. 48 khz sampling rate a-weighted, both channels active 12 mhz master clock. 48 khz sampling rate differential output at line-out, 1k ? load. both channels active -120 -100 -80 -60 -40 -20 0 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k amplitude [dbfs] frequency [hz] 20 30 40 50 60 70 80 90 100 -60 -50 -40 -30 -20 -10 0 s/n [db] input level [dbfs] 12 mhz master clock. 48 khz sampling rate differential output at line-out, 1k ? load. a-weighted, both channels active -120 -100 -80 -60 -40 -20 0 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k amplitude [dbfs] frequency [hz] differential input at mic preamplifier, 21 db gain. direct mic to line-out connection (miclo=1) differential output at line-out, 20k ? load. both channels active 20 30 40 50 60 70 80 90 100 -60 -50 -40 -30 -20 -10 0 s/n [db] input level [dbfs] differential input at line-in amplifier, 0 db gain. line-in to da-mixer to line-out connection. differential output at line-out, 20k ? load. a-weighted, both channels active .com .com .com .com 4 .com u datasheet
17 application schematics STW5095 66/69 17 application schematics figure 31. STW5095 application schematics as/csb 200nf capmic 0.47 f aux2rn aux2rp aux1l ockda vccio gnd vcc gndcm vccp gndp gnda vcca 10 f vcmhp da_ck amck da_sync da_data sda/sdin sclk 100nf 100nf 8 ? typ lsp lsn 10 f caplinein hpr hpl 0.47 f aux3r 0.47 f aux3l mic1ln 10 f 2.7k ? 750 ? 100nf 100nf 750 ? 2.7k ? mic1lp mbias fm in vcca 1 f 100nf 100nf vccd STW5095 electret system clock [4mhz-32mhz] clock data da_ data da_ data clock audio data interface i2c compat. bus vccp 0.47 f 0.47 f aux1r voice in aux2lp melody in mic1rn 10 f 2.7k ? 750 ? 100nf 100nf 750 ? 2.7k ? mic1rp electret capls 10 f lsps lsns sense sense aux2ln da_ fs [8khz-48khz] [88khz-96khz] ad_ck ad_sync ad_data ad_data ad_data clock ad_fs [8khz-48khz] [88khz-96khz] ockad masterclocks for other digital device vcmhps 100nf line in 100nf lineinl lineinr 500mw max. 16 /32? typ 40mw max. vccls l olp oln r orp orn line out l r l r cmod i 2 c compat. bus selected to have a single bidirectional interface connect: ad_sync to da_sync ad_ck to da_ck differential connector standard hp connection d/a audio data interface a/d vccio sense hdet irq as close as possible to the pins as close as possible to the pins needed if irq vccio or for digital audio data source leave the negative pins unconnected when used in single-ended configuration 100pf see application example in section 3.16 on page 19 is not set to cmos .com .com .com .com 4 .com u datasheet
STW5095 18 package outline 67/69 18 package outline note: 1 the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. dimensions [mm] outline and mechanical data ref. min. typ. max. a (1) 1. the total profile height is measured from the seating plane to the top of the component. 1.010 1.200 (2) 2. max mounted height is 1.12mm.based on a 0.28mm ball pad diameter. solder paste is 0.15mm thickness and 0.28mm diameter. a1 0.150 a2 0.820 b 0.250 0.300 0.350 d 4.850 5.000 5.150 d1 3.500 e 4.850 5.000 5.150 e1 3.500 e 0.450 0.500 0.550 f 0.600 0.750 0.900 tfbga 5x5x1.20 64 f8x8 0.50 t hin profile f ine pitch b all g rid a rray ddd 0.080 figure 32. package mechanical data f ddd c c a1 a a2 ef d1 e1 e e d h g f e d c b a 12345678 a1 corner index area ?b (64 balls) plane seating bottom view see note 1 .com .com .com .com 4 .com u datasheet
19 revision history STW5095 68/69 19 revision history date revision changes 8-nov-2005 1.0 initial release .com .com .com .com 4 .com u datasheet
STW5095 69/69 information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com .com .com .com 4 .com u datasheet

▲Up To Search▲

Price & Availability of STW5095

	To Download STW5095 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .